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System Control
ARM DDI 0363G Copyright © 2006-2011 ARM Limited. All rights reserved. 4-40
ID073015 Non-Confidential
4.3.16 c1, Auxiliary Control Register
The ACTLR characteristics are:
Purpose Controls:
branch prediction
performance features
error and parity logic.
Usage constraints The ACTLR is:
a read/write register
accessible in Privileged mode only
ARM recommends that any instruction that changes bits [31:28] or
[7] is followed by an
ISB
instruction to ensure that the changes have
taken effect before any dependent instructions are executed.
Configurations Available in all processor configurations.
Attributes See Table 4-24 on page 4-41.
Figure 4-27 shows the ACTLR bit assignments.
Figure 4-27 ACTLR Register bit assignments
31 25 24 23
22
21
19 18
17
16 15 14 13 12 11 7 6 3 2 1 0
CEC
26272830 29
DIADI
1020
DICDI
DIB2DI
DIB1DI
B1TCMPCEN
B0TCMPCEN
ATCMPCEN
AXISCEN
9
BP
58
AXISCUEN
DILSM
DEOLP
DBHE
FRCDIS RSDIS
Reserved
ATCMECEN
B0TCMECEN
B1TCMECEN
DILS
sMOV
FDSnS
FWT
FORA
DNCH
ERPEG
DLFO
DBWR

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