ARM Cortex-R4 - Page 111

System Control
ARM DDI 0363G Copyright © 2006-2011 ARM Limited. All rights reserved. 4-41
ID073015 Non-Confidential
Table 4-24 shows the ACTLR bit assignments.
Table 4-24 ACTLR Register bit assignments
Bits Name Function
[31]
DICDI
a
Case C dual issue control:
0 = Enabled. This is the reset value.
1 = Disabled.
[30]
DIB2DI
a
Case B2 dual issue control:
0 = Enabled. This is the reset value.
1 = Disabled.
[29]
DIB1DI
a
Case B1 dual issue control:
0 = Enabled. This is the reset value.
1 = Disabled.
[28]
DIADI
a
Case A dual issue control:
0 = Enabled. This is the reset value.
1 = Disabled.
[27] B1TCMPCEN B1TCM parity or ECC check enable:
0 = Disabled
1 = Enabled.
The primary input PARECCENRAM[2]
b
defines the reset value.
If the BTCM is configured with ECC, you must always set this bit to the same value as
B0TCMPCEN.
[26] B0TCMPCEN B0TCM parity or ECC check enable:
0 = Disabled
1 = Enabled.
The primary input PARECCENRAM[1]
b
defines the reset value.
If the BTCM is configured with ECC, you must always set this bit to the same value as
B1TCMPCEN.
[25] ATCMPCEN ATCM parity or ECC check enable:
0 = Disabled
1 = Enabled.
The primary input PARECCENRAM[0]
b
defines the reset value.
[24] AXISCEN AXI slave cache RAM access enable:
0 = Disabled. This is the reset value.
1 = Enabled.
Note
When AXI slave cache access is enabled, the caches are disabled and the processor cannot
run any cache maintenance operations. If the processor attempts a cache maintenance
operation, an Undefined Instruction exception is taken.
[23] AXISCUEN AXI slave cache RAM non-privileged access enable:
0 = Disabled. This is the reset value.
1 = Enabled.
[22] DILSM Disable Low Interrupt Latency (LIL) on load/store multiples:
0 = Enable LIL on load/store multiples. This is the reset value.
1 = Disable LIL on all load/store multiples.