Need help?Do you have a question about the ARM Cortex-R4 and is the answer not in the manual?
General| Architecture | ARMv7-R |
|---|---|
| Bit Width | 32-bit |
| Memory Protection | Memory Protection Unit (MPU) |
| Pipeline | 8-stage |
| Floating Point Unit | Optional VFPv3 |
| Endianness | Configurable (Little or Big Endian) |
| ISA | Thumb-2 |
| Interrupt Controller | Yes |
| Tightly Coupled Memory (TCM) | Yes |
| Typical Applications | Automotive |
| Cores | Single-core |
| Cache | Optional instruction and data cache (4-64 KB) |
Provides an overview of the Cortex-R4 processor and its architecture.
Details the ARM architecture, trace macrocell, AMBA, and debug architecture compliance.
Lists the key features of the Cortex-R4 processor, including its units and interfaces.
Describes the various interfaces the processor provides for external connections.
Details the features that can be configured during build or pin configuration.
Explains the test features available for production testing and implementation.
Describes the processor documentation, design flow, and related standards.
Outlines the functional differences between product revisions r1p3 and r1p4.
Describes the main components of the processor, including DPU, LSU, PFU, and memory systems.
Lists the processor's external interfaces, including AXI, TCM, and debug interfaces.
Explains the processor's clock inputs and reset signals and modes.
Describes processor operation, including initialization requirements for MPU, FPU, and caches.
Introduces the ARMv7 architecture implemented by the processor and instruction sets.
Details the processor's instruction set states (ARM/Thumb) and operating modes.
Explains memory organization, byte-invariant big-endian, and little-endian formats.
Describes supported data types (doubleword, word, halfword, byte) and alignment.
Details the processor's register set, including general-purpose and special-function registers.
Explains the CPSR and SPSRs, their bit assignments, and modification by MSR instructions.
Covers exception handling, entry/exit summaries, and types of exceptions like resets and aborts.
Provides an overview of the system control coprocessor (CP15) and its functions.
Lists the system control coprocessor's registers and their functions grouped by category.
Provides detailed descriptions of CP15 registers, including their addresses and operations.
Describes the PreFetch Unit (PFU), functionality, and interaction with DPU.
Explains the dynamic branch prediction scheme and its two major classes of branches.
Details the call-return stack mechanism for predicting procedure returns.
Explains how to control prefetch and program flow prediction using ACTLR bits.
Introduces events detected by the processor for debugging and profiling.
Describes the Performance Monitoring Unit (PMU) components and accessibility.
Lists and describes registers for controlling and interrogating performance counters.
Explains the MPU's role in memory access control and region partitioning.
Defines memory types (Strongly-ordered, Device, Normal) and their attributes.
Details attributes associated with memory regions, controlling memory access behavior.
Describes how to enable and disable the MPU, including pipeline flushing.
Explains the types of faults generated by the MPU: background, permission, and alignment.
Describes the L1 memory system, including caches, TCMs, and the MPU.
Explains error detection and correction schemes like parity and ECC for memory.
Discusses how the processor handles various faults, including MPU faults and external errors.
Details the TCM interfaces, configuration, and internal error detection mechanisms.
Explains the L1 cache organization, maintenance operations, and error detection.
Describes events related to internal error detection and correction in TCMs and caches.
Describes the processor's L2 interface, consisting of AXI master and slave interfaces.
Details the AXI master interface, including signals, attributes, and transfer types.
Explains the types of AXI bursts generated by the processor and transfer restrictions.
Describes the AXI slave interface for accessing TCMs and cache RAMs.
Provides examples for enabling and disabling AXI slave accesses to cache RAMs.
Explains how to access TCM and cache RAMs using the AXI slave interface.
Describes processor features that improve energy efficiency, like branch prediction and clock gating.
Details the four power management levels: Run, Standby, Dormant, and Shutdown modes.
Introduces the FPU's VFPv3-D16 architecture and its IEEE 754 compliance.
Describes the VFP register bank views: D0-D15 and S0-S31.
Explains VFP system registers like FPSID, FPSCR, FPEXC, and MVFR.
Details the FPU's compliance with the IEEE 754 standard and implementation choices.
Outlines the typical components of a debug system: host, protocol converter, and target.
Describes the processor debug unit's capabilities and debugging modes.
Explains accessing debug registers via APB slave port and coprocessor interface.
Provides detailed descriptions of CP14 and memory-mapped debug registers.
Lists software debug events like watchpoints, breakpoints, and vector catches.
Explains how the processor handles debug exceptions and their effects on registers.
Describes the processor's behavior and register access while in debug state.
Details cache pollution, coherency, and usage profiling in debug state.
Covers APB signals, miscellaneous debug signals, and authentication signals.
Provides examples of using debug functionality, including instruction execution and register access.
Discusses debugging systems with energy-saving measures and emulating power down.
Introduces Integration Test Registers for verifying design integration and topology detection.
Lists integration test registers and the Integration Mode Control Register (DBGITCTRL).
Describes the use of Integration Test Registers for controlling outputs and reading inputs.
Explains the format of processor signal descriptions, including direction, clocking, and meaning.
Lists and describes the processor's global signals, including clocks and reset.
Details the processor's configuration signals for customizing behavior at reset.
Lists and describes interrupt signals, including those for the VIC interface.
Describes the AXI master and slave interface signals for the L2 interface.
Lists and describes signals for the ATCM and BTCM interfaces.
Describes the interface signals for dual redundant core configurations.
Lists and describes signals related to the APB interface and miscellaneous debug signals.
Lists and describes signals for the ETM interface.
Lists and describes signals used for design-for-test (DFT).
Lists and describes signals related to Memory Built-In Self Test (MBIST).
Lists and describes signals used for system validation purposes.
Lists and describes signals specific to the Floating Point Unit (FPU).
States that the AXI and APB interfaces conform to their respective protocol specifications.
Describes input and output port timing parameters as percentages of the processor clock cycle.
Explains that precise timings require a cycle-accurate model and describes best-case assumptions.
Provides examples of register interlocks using LDR and ADD instructions.
Describes cycle timing for data processing instructions, distinguishing between PC and non-PC destinations.
Details the cycle timing behavior of saturating arithmetic instructions.
Provides cycle timing for media data-processing instructions, noting single-cycle issue and result latencies.
Shows cycle timing and interlock examples for SAD and SAD8 instructions.
Describes cycle timing for multiply operations, including early forwarding and interlocks.
Explains the cycle timing behavior for UDIV and SDIV instructions, including result latency formulas.
Details cycle timing for branch instructions, including predictions and condition code handling.
Describes cycle timing for instructions that update processor state like MRS, MSR, CPS, SETEND.
Covers cycle timing for single load/store instructions, noting alignment and register requirements.
Details cycle timing for LDRD and STRD instructions, considering alignment and writeback.
Explains cycle timing for LDM, STM, PUSH, and POP instructions, including PC loading.
Describes cycle timing for RFE and SRS instructions used for exception return.
Covers cycle timing for synchronization instructions like LDREX, STREX, DMB, DSB, ISB.
Details cycle timing for MCR and MRC instructions used with coprocessors CP14 and CP15.
Provides cycle timing for exception-generating instructions.
Describes cycle timing for IT, NOP, WFI, and SEV instructions.
Details cycle timing for VFP instructions transferring data between register files.
Covers cycle timing for VFP load/store instructions, considering alignment and writeback.
Provides cycle timing for single-precision VFP arithmetic and comparison instructions.
Details cycle timing for double-precision VFP arithmetic and comparison instructions.
Explains dual-issue rules and permitted instruction combinations for increased throughput.
Describes ECC schemes for TCM interfaces and provides guidelines for selection.
To Next Page
