ARM Cortex-R4 - Appendix C Cycle Timings and Interlock Behavior

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Appendix C
Cycle Timings and Interlock Behavior
This chapter describes the cycle timings and interlock behavior of instructions on the processor. It
contains the following sections:
• About cycle timings and interlock behavior on page C-3
• Register interlock examples on page C-6
• Data processing instructions on page C-7
• QADD, QDADD, QSUB, and QDSUB instructions on page C-9
• Media data-processing on page C-10
• Sum of Absolute Differences (SAD) on page C-11
• Multiplies on page C-12
• Divide on page C-14
• Branches on page C-15
• Processor state updating instructions on page C-16
• Single load and store instructions on page C-17
• Load and Store Double instructions on page C-20
• Load and Store Multiple instructions on page C-21
• RFE and SRS instructions on page C-24
• Synchronization instructions on page C-25
• Coprocessor instructions on page C-26
• SVC, BKPT, Undefined, and Prefetch Aborted instructions on page C-27
• Miscellaneous instructions on page C-28
• Floating-point register transfer instructions on page C-29
• Floating-point load/store instructions on page C-30
• Floating-point single-precision data processing instructions on page C-32