AC Characteristics
ARM DDI 0363G Copyright © 2006-2011 ARM Limited. All rights reserved. B-13
ID073015 Non-Confidential
The timing parameters for the dual-redundant core compare logic output buses,
DCCMOUT[7:0] and DCCMOUT2[7:0], are implementation-defined. Contact the
implementer of the macrocell you are working with.
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