Memory Protection Unit
ARM DDI 0363G Copyright © 2006-2011 ARM Limited. All rights reserved. 7-11
ID073015 Non-Confidential
7.6 MPU software-accessible registers
Figure 4-2 on page 4-3 shows the CP15 registers that control the MPU.
When the MPU is not present, the c6, MPU memory region programming registers on page 4-51
read as zero and ignore writes in Privileged mode. No Undefined Instruction exceptions are
taken.
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