System Control
ARM DDI 0363G Copyright © 2006-2011 ARM Limited. All rights reserved. 4-3
ID073015 Non-Confidential
4.1.2 MPU control and configuration
The MPU control and configuration registers:
• control program access to memory
• designate areas of memory as either:
— Normal, non-cacheable
— Normal, cacheable
—Device
— Strongly-ordered.
• detect MPU faults and external aborts.
The MPU control and configuration registers consist of one read-only register and eleven
read/write registers. Figure 4-2 shows the arrangement of registers in this functional group.
Figure 4-2 MPU control and configuration registers
4.1.3 Cache control and configuration
The cache control and configuration registers:
• provide information on the size and architecture of the instruction and data caches
• control cache maintenance operations that include clean and invalidate caches, drain and
flush buffers, and address translation
• override cache behavior during debug or interruptible cache operations.
The cache control and configuration registers consist of three read-only registers, one read/write
register, and a number of write-only registers. Figure 4-3 on page 4-4 shows the arrangement of
the registers in this functional group.
4
c00
Opcode_2CRmCRn Opcode_1
1
Data Fault Address Register
Data Fault Status Register
0
0
c5
Region Size and Enable Register
Region Base Register
Region Access Control Register
Memory Region Number Register
Instruction Fault Address Register
Instruction Fault Status Register
1
Auxilary Data Fault Status Register
Auxilary Instruction Fault Status Register
0
c0
0 c0
c1
c6
0 c0
0
c1
2
4
0
c2
2
Write-only
Accessible in User mode
Read-only Read/write
0
Correctable Fault Location Registerc15
c30
MPU Type Register
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