System Control
ARM DDI 0363G Copyright © 2006-2011 ARM Limited. All rights reserved. 4-4
ID073015 Non-Confidential
Figure 4-3 Cache control and configuration registers
4.1.4 Interface control and configuration
The interface control and configuration registers:
• indicate the size, number and status of the TCM regions
• define and enable TCM regions
• indicate the size and address of the peripheral interface regions
• enable the peripheral interface regions
• control AXI slave interface permissions.
The interface control and configuration registers consist of two read-only registers and two
read/write registers. Figure 4-4 shows the arrangement of registers.
Figure 4-4 TCM control and configuration registers
4.1.5 System performance monitor
The performance monitor registers:
• control the monitoring operation
• count events.
The system performance monitor consists of 12 read/write registers. Figure 4-5 on page 4-5
shows the arrangement of registers in this functional group.
Opcode_2CRmOpcode_1
1
c0 0 c0 Cache Type Register
CRn
c7
† Cache Operations Registers ‡
‡ See description of cache operations
for operations with User mode access
Invalidate all Data Cache Registerc15
0
0
0 c5
Write-only
Accessible in User mode
Read-only Read/write
Current Cache Size Identification Register
Current Cache Level Identification Register
Cache Size Selection Register
0
c01
1
0
2 c0
†
† See description of cache operations for
implemented CRm and Opcode_2 values
ATCM Region Register
1
c9
0
c0
2
0
0
c0
BTCM Region Register
TCM Type Register
CRn CRmOpcode_1 Opcode_2
TCM Selection Register
0
Write-only
Accessible in User mode
Read-only
Read/write
c1
c2
Slave Port Control Register
0
c11
0 c0
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