ARM DDI 0363G Copyright © 2006-2011 ARM Limited. All rights reserved. 8-1
ID073015 Non-Confidential
Chapter 8
Level One Memory System
This chapter describes the processor Level one (L1) memory system. It contains the following
sections:
• About the L1 memory system on page 8-2
• About the error detection and correction schemes on page 8-4
• Fault handling on page 8-7
• About the TCMs on page 8-13
• About the caches on page 8-18
• Internal exclusive monitor on page 8-34
• Memory types and L1 memory system behavior on page 8-35
• Error detection events on page 8-36.
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