ARM Cortex-R4 - 6.3 Performance monitoring registers

Events and Performance Monitor
ARM DDI 0363G Copyright © 2006-2011 ARM Limited. All rights reserved. 6-7
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6.3 Performance monitoring registers
The following sections describe the performance monitoring registers:
• c9, Performance Monitor Control Register
• c9, Count Enable Set Register on page 6-8
• c9, Count Enable Clear Register on page 6-9
• c9, Overflow Flag Status Register on page 6-11
• c9, Software Increment Register on page 6-12
• c9, Performance Counter Selection Register on page 6-13
• c9, Cycle Count Register on page 6-13
• c9, Event Type Selection Register on page 6-14
• c9, Event Count Registers on page 6-15
• c9, User Enable Register on page 6-15
• c9, Interrupt Enable Set Register on page 6-16
• c9, Interrupt Enable Clear Register on page 6-17.
6.3.1 c9, Performance Monitor Control Register
The PMCR Register characteristics are:
Purpose Controls the operation of the three count registers, and the PMCCNTR
Register.
Usage constraints The PMCR Register is:
• a read/write register
• accessible in:
— Privileged mode
— User mode only when the PMUSERENR.EN bit is set to 1,
see c9, User Enable Register on page 6-15.
Configurations Available in all processor configurations.
Attributes See Table 6-2 on page 6-8.
Figure 6-1 shows the PMCR bit assignments.
Figure 6-1 PMCR Register bit assignments
D C P EIMP
31 11 6 4 3 2 1 0
IDCODE N
10
Reserved
D
P
5
X
24 23 16 15