Events and Performance Monitor
ARM DDI 0363G Copyright © 2006-2011 ARM Limited. All rights reserved. 6-8
ID073015 Non-Confidential
Table 6-2 shows the PMCR bit assignments.
The PMCR Register is always accessible in Privileged mode. To access the register, read or
write CP15 with:
MRC p15, 0, <Rd>, c9, c12, 0 ; Read PMCR Register
MCR p15, 0, <Rd>, c9, c12, 0 ; Write PMCR Register
6.3.2 c9, Count Enable Set Register
The PMCNTENSET Register characteristics are:
Purpose Enables the Event Count Registers.
Usage constraints The PMCNTENSET Register is:
• accessible in:
— Privileged mode
— User mode only when the PMUSERENR.EN bit is set to 1,
see c9, User Enable Register on page 6-15.
Table 6-2 PMCR Register bit assignments
Bits Name Function
[31:24] IMP Implementer code:
0x41
= ARM
[23:16] IDCODE Identification code:
0x14
= Cortex-R4
[15:11] N Specifies the number of counters implemented:
0x3
= three counters implemented
[10: 6] - RAZ on reads, Should Be Zero or Preserved (SBZP) on writes
[5] DP Disable PMCCNTR when prohibited, that is, when non-invasive debug is not enabled:
0 = Count is enabled in prohibited regions. This is the reset value.
1 = Count is disabled in prohibited regions.
[4] X Enable export of the events to the event bus for an external monitoring block, for example the
ETM, to trace events:
0 = Export disabled. This is the reset value.
1 = Export enabled.
[3] D Cycle count divider:
0 = Counts every processor clock cycle. This is the reset value.
1 = Counts every 64th processor clock cycle.
[2] C Cycle counter reset:
Write one to this bit to reset the cycle counter, PMCCNTR, to zero.
This bit Reads-As-Zero.
[1] P Event counter reset:
Write one to this bit to reset all event counters to zero.
This bit Reads-As-Zero.
[0] E Enable:
0 = Disable all counters, including PMCCNTR. This is the reset value.
1 = Enable all counters including PMCCNTR.
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