Events and Performance Monitor
ARM DDI 0363G Copyright © 2006-2011 ARM Limited. All rights reserved. 6-16
ID073015 Non-Confidential
Figure 6-8 PMUSERENR Register bit assignments
Table 6-9 shows the PMUSERENR bit assignments.
If the EN bit in the PMUSERENR register is not set, any attempt to access a performance
monitor register or a validation register from User mode causes an Undefined Instruction
exception.
For more information on access permissions to the performance monitor registers and validation
registers, see the ARM Architecture Reference Manual.
To access the PMUSERENR register, read or write CP15 with:
MRC p15, 0, <Rd>, c9, c14, 0 ; Read PMUSERENR Register
MCR p15, 0, <Rd>, c9, c14, 0 ; Write PMUSERENR Register
6.3.11 c9, Interrupt Enable Set Register
The PMINTENSET Register characteristics are:
Purpose Determines if any of the PMXEVCNTR Registers,
PMXEVCNTR0-PMXEVCNTR2 and PMCCNTR, generate an interrupt
request on overflow.
Usage constraints The PMINTENSET Register is:
• a read/write register
• accessible in Privileged mode only.
Configurations Available in all processor configurations.
Attributes See Table 6-10 on page 6-17.
Figure 6-9 on page 6-17 shows the PMINTENSET bit assignments.
Table 6-9 PMUSERENR Register bit assignments
Bits Name Function
[31:1] - RAZ or SBZP.
[0] EN User mode access to performance monitor and validation registers:
0 = Disabled. This is the reset value.
1 = Enabled.
To Next Page
Loading...
