Events and Performance Monitor
ARM DDI 0363G Copyright © 2006-2011 ARM Limited. All rights reserved. 6-12
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6.3.5 c9, Software Increment Register
The PMSWINC Register characteristics are:
Purpose Increments the count of an Event Count Register.
Usage constraints The PMSWINC Register is:
• A write-only register that Reads-As-Zero
• Accessible in:
— Privileged mode
— User mode only when the PMUSERENR.EN bit is set to 1,
see c9, User Enable Register on page 6-15.
• You must only use the PMSWINC Register to increment Event
Count Registers when the counter event is set to
0x00
, software
count, in the Event Select Register, see c9, Event Type Selection
Register on page 6-14.
• If you attempt to use the PMSWINC Register to increment an Event
Count Register when the counter event is set to a value other than
0x00
the result is Unpredictable.
Configurations Available in all processor configurations.
Attributes See Table 6-6.
Figure 6-5 shows the PMSWINC bit assignments.
Figure 6-5 PMSWINC Register bit assignments
Table 6-6shows the PMSWINC bit assignments.
To access the PMSWINC Register, read or write CP15 with:
MRC p15, 0, <Rd>, c9, c12, 4 ; Read PMSWINC Register
MCR p15, 0, <Rd>, c9, c12, 4 ; Write PMSWINC Register
31 3210
Reserved
P2
P1
P0
Performance monitor counters
software increment bits
Table 6-6 PMSWINC Register bit assignments
Bits Name Function
[31:3] - RAZ on reads, SBZP on writes
[2] P2 Increment Counter 2
[1] P1 Increment Counter 1
[0] P0 Increment Counter 0
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