Events and Performance Monitor
ARM DDI 0363G Copyright © 2006-2011 ARM Limited. All rights reserved. 6-14
ID073015 Non-Confidential
• Is accessible in:
— Privileged mode
— User mode only when the PMUSERENR.EN bit is set to 1,
see c9, User Enable Register on page 6-15.
• Must be disabled before software can write to it. Any attempt by
software to write to this register when enabled is Unpredictable.
Configurations Available in all processor configurations.
To access the PMCCNTR read or write CP15 with:
MRC p15, 0, <Rd>, c9, c13, 0 ; Read PMCCNTR Register
MCR p15, 0, <Rd>, c9, c13, 0 ; Write PMCCNTR Register
The PMCCNTR register must be disabled before software can write to it. Any attempt by
software to write to this register when enabled is Unpredictable.
6.3.8 c9, Event Type Selection Register
The processor has three Event Type Select Registers, PMXEVTYPER0 to PMXEVTYPER2,
each corresponding to one of the Performance Monitor Count (PMXEVCNTR) Registers,
PMXEVCNTR0 to PMXEVCNTR2. The value in PMSELR determines access to these
registers.
The PMXEVTYPER Register characteristics are:
Purpose Selects the events you want a PMXEVCNTR Register to count.
Usage constraints The PMXEVTYPER Register is:
• A read/write register
• Accessible in:
— Privileged mode
— User mode only when the PMUSERENR.EN bit is set to 1,
see c9, User Enable Register on page 6-15.
Configurations Available in all processor configurations.
Attributes See Table 6-8.
Figure 6-7 shows the PMXEVTYPER bit assignments.
Figure 6-7 PMXEVTYPERx Register bit assignments
Table 6-8 shows the PMXEVTYPER bit assignments.
Table 6-8 PMXEVTYPERx Register bit assignments
Bits Name Function
[31:8] - RAZ or SBZP.
[7:0] SEL Event number selected, see Table 6-1 on page 6-2 for values.
The reset value of this field is Unpredictable.
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