Events and Performance Monitor
ARM DDI 0363G Copyright © 2006-2011 ARM Limited. All rights reserved. 6-11
ID073015 Non-Confidential
6.3.4 c9, Overflow Flag Status Register
The PMOVSR Register characteristics are:
Purpose Indicates if event counters have overflowed. All overflow flags are reset
to zero.
Usage constraints The PMOVSR Register is accessible in:
• Privileged mode
• User mode only when the PMUSERENR.EN bit is set to 1, see c9,
User Enable Register on page 6-15.
Configurations Available in all processor configurations.
Attributes See Table 6-5.
Figure 6-4 shows the PMOVSR bit assignments.
Figure 6-4 PMOVSR Register bit assignments
Table 6-5 shows the PMOVSR bit assignments.
To access the PMOVSR, read or write CP15 with:
MRC p15, 0, <Rd>, c9, c12, 3 ; Read PMOVSR
MCR p15, 0, <Rd>, c9, c12, 3 ; Write PMOVSR
If an overflow flag is set to 1 in the PMOVSR it remains set until one of the following happens:
• writing 1 to the flag bit in the PMOVSR clears the flag
• the processor is reset.
The following operations do not clear the overflow flags:
• disabling the overflowed counter in the PMCNTENCLR Register
• disabling all counters in the PMCR Register
• resetting the overflowed counter using the PMCR Register.
C
31 3210
Reserved
P2
P1
P0
Performance monitor counters
overflow flags
Cycle count overflow
Table 6-5 PMOVSR Register bit assignments
Bits Name Function
[31] Cycle counter overflow Cycle counter overflow flag
[30:3] - UNP on reads, SBZP on writes
[2] P2 Counter 2 overflow flag
[1] P1 Counter 1 overflow flag
[0] P0 Counter 0 overflow flag
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