Events and Performance Monitor
ARM DDI 0363G Copyright © 2006-2011 ARM Limited. All rights reserved. 6-10
ID073015 Non-Confidential
— User mode only when the PMUSERENR.EN bit is set to 1,
see c9, User Enable Register on page 6-15.
Configurations Available in all processor configurations.
Attributes See Table 6-4.
Figure 6-3 shows the PMCNTENCLR bit assignments.
Figure 6-3 PMCNTENCLR Register bit assignments
Table 6-4 shows the PMCNTENCLR bit assignments.
To access the PMCNTENCLR Register, read or write CP15 with:
MRC p15, 0, <Rd>, c9, c12, 2 ; Read PMCNTENCLR Register
MCR p15, 0, <Rd>, c9, c12, 2 ; Write PMCNTENCLR Register
When reading this register, any enable that reads as 0 indicates the corresponding counter is
disabled. Any enable that reads as 1 indicates the corresponding counter is enabled.
When writing this register, any enable written with a value of 0 is ignored, that is, not updated.
Any enable written with a value of 1 clears the counter enable. You must use the Count Enable
Set Register to enable the counters. All counters are disabled at reset.
Writing to bits in this register disables individual counters, and clears the corresponding bits in
the PMCNTENSET Register, see c9, Count Enable Set Register on page 6-8.
You can use the enable, EN, bit [0] of the PMCR Register to disable all performance counters
including PMCCNTR, see c9, Performance Monitor Control Register on page 6-7.
The PMCNTENCLR and PMCNTENSET Registers retain their values when the enable bit of
the PMCR is clear, even though their settings are ignored. The PMCNTENCLR Register can be
used to clear the enabled flags for individual counters even when all counters are disabled in the
PMCR Register.
C
31 3210
Reserved
P2
P1
P0
Performance monitor
counter disables
Cycle count disable
Table 6-4 PMCNTENCLR Register bit assignments
Bits Name Function
[31] C Cycle counter disable
[30:3] - UNP on reads, SBZP on writes
[2] P2 Counter 2 enable
[1] P1 Counter 1 enable
[0] P0 Counter 0 enable
To Next Page
Loading...
