ARM Cortex-R4 - B.1 Processor timing

AC Characteristics
ARM DDI 0363G Copyright © 2006-2011 ARM Limited. All rights reserved. B-2
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B.1 Processor timing
The AXI bus interface of the processor conforms to the AMBA AXI Specification. For the
relevant timing of the AXI write and read transfers, and the error response, see the AMBA AXI
Protocol Specification.
The APB debug interface of the processor conforms to the AMBA 3 APB Protocol Specification.
For the relevant timing of the APB write and read transfers, and the error response, see the
AMBA 3 APB Protocol Specification.