System Control
ARM DDI 0363G Copyright © 2006-2011 ARM Limited. All rights reserved. 4-37
ID073015 Non-Confidential
Configurations Available in all processor configurations.
Attributes See Table 4-22.
Figure 4-25 shows the CSSELR bit assignments.
Figure 4-25 CSSELR Register bit assignments
Table 4-22 shows the CSSELR bit assignments.
To access the CCSIDRs read or write CP15 with:
MRC p15, 2, <Rd>, c0, c0, 0 ; Read CSSELR
MCR p15, 2, <Rd>, c0, c0, 0 ; Write CSSELR
4.3.15 c1, System Control Register
The SCTLR characteristics are:
Purpose Provides control and configuration information for:
• memory alignment, endianness, protection, and fault behavior
• MPU and cache enables and cache replacement strategy
• interrupts and the behavior of interrupt latency
• the location for exception vectors
• program flow prediction.
Usage constraints The SCTLR is:
• a read/write register
• accessible in Privileged mode only
• attempts to read or write the SCTLR from User mode result in an
Undefined Instruction exception.
Configurations Available in all processor configurations.
Attributes See Table 4-23 on page 4-38.
Figure 4-26 on page 4-38 shows the SCTLR bit assignments.
Table 4-22 CSSELR Register bit assignments
Bits Name Function
[31: 4] - SBZ.
[3:1] Level Identifies which cache level to select:
b000
= L1 cache
This field is read only, writes are ignored.
[0] InD Identifies instruction or data cache to use:
1
= instruction
0
= data.
To Next Page
Loading...
