Integration Test Registers
ARM DDI 0363G Copyright © 2006-2011 ARM Limited. All rights reserved. 13-5
ID073015 Non-Confidential
This section describes:
• Using the Integration Test Registers
• Performing integration testing
• DBGITETMIF Register (ETM interface) on page 13-6
• DBGITMISCOUT Register (Miscellaneous Outputs) on page 13-7
• DBGITMISCIN Register (Miscellaneous Inputs) on page 13-7
• Integration Mode Control Register on page 13-8.
13.3.1 Using the Integration Test Registers
When bit [0] of the Integration Mode Control Register, DBGITCTRL, is set to b1:
• Values written to the write-only Integration Test Registers map onto the specified outputs
of the macrocell. For example, writing
b1
to DBGITMISCOUT[0] causes DBGACK to
be asserted HIGH.
• Values read from the read-only Integration Test Registers correspond to the values of the
specified inputs of the macrocell. For example, if you read DBGITMISCIN[9:8] you
obtain the value of ETMEXTOUT[1:0].
13.3.2 Performing integration testing
When you perform integration testing or topology detection:
• You must ensure that the other ETM interface signals cannot change value during
integration testing.
• ARM strongly recommends that the processor is halted while in debug state, because
toggling input and output pins might have an unwanted effect on the operation of the
processor. You must not set the DBGITCTRL Register until the processor has halted.
When the DBGITCTRL Register is set, the ETM interface stops trace output, and outputs
the data written into the relevant integration registers.
After you perform integration testing or topology detection, that is, the Integration Mode
Control Register is set, the system must be reset. This is because the signals that are toggled can
have an unwanted effect on connected devices.
Table 13-3 Input signals that can be read by the Integration Test Registers
Signal Register Bit Register description
DBGRESTART DBGITMISCIN [11] See DBGITMISCIN Register (Miscellaneous Inputs) on page 13-7
ETMEXTOUT[1:0] DBGITMISCIN [9:8]
nETMWFIREADY DBGITMISCIN [5]
nIRQ DBGITMISCIN [2]
nFIQ DBGITMISCIN [1]
EDBGRQ DBGITMISCIN [0]
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