ARM Cortex-R4 - Page 312

Debug
ARM DDI 0363G Copyright © 2006-2011 ARM Limited. All rights reserved. 12-38
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12.5.3 Lock Access Register
The DBGLAR is a write-only register that controls writes to the debug registers. The purpose
of the DBGLAR is to reduce the risk of accidental corruption to the contents of the debug
registers. It does not prevent all accidental or malicious damage. Because the state of the
DBGLAR is in the debug power domain, it is not lost when the processor powers down.
DBGLAR [31:0] contain a key that controls the lock status. To unlock the debug registers, write
a
0xC5ACCE55 key to this register. To lock the debug registers, write any other value. Accesses to
locked debug registers are ignored. The lock is set on reset.
12.5.4 Lock Status Register
The DBGLSR Register characteristics are:
Purpose Returns the current lock status of the debug registers.
Usage constraints The DBGLSR is:
• a read-only register
• only defined in the memory-mapped interface
Configurations Available in all processor configurations.
Attributes See Table 12-29.
Figure 12-18 shows the DBGLSR bit assignments.
Figure 12-18 DBGLSR Register bit assignments
Table 12-29 shows the DBGLSR bit assignments.
12.5.5 Device Type Register
The DBGDEVTYPE Register characteristics are:
Purpose Indicates the type of debug component.
31
31 0
Reserved
123
32-bit access
Locked bit
Lock implemented bit
Table 12-29 DBGLSR Register bit assignments
Bits Name Function
[31:3] - Do not modify on writes. On reads, the value returns zero.
[2] 32-bit access Indicates that a 32-bit access is required to write the key to the Lock Access Register.
This bit always reads 0.
[1] Locked bit Locked bit:
0 = Writes are permitted.
1 = Writes are ignored. This is the reset value.
[0] Lock implemented bit Indicates that the OS lock functionality is implemented. This bit always reads 1.