Debug
ARM DDI 0363G Copyright © 2006-2011 ARM Limited. All rights reserved. 12-39
ID073015 Non-Confidential
Usage constraints The DBGDEVTYPE Register is a read-only register.
Configurations Available in all processor configurations.
Attributes See Table 12-30.
Figure 12-19 shows the DBGDEVTYPE bit assignments.
Figure 12-19 DBGDEVTYPE Register bit assignments
Table 12-30 shows the DBGDEVTYPE bit assignments.
12.5.6 Debug Identification Registers
The Debug Identification Registers are read-only registers that consist of the Peripheral
Identification Registers and the Component Identification Registers. The Peripheral
Identification Registers provide standard information that all CoreSight components require.
Only bits [7:0] of each register are used. The remaining bits Read-As-Zero.
The Component Identification Registers identify the processor as a CoreSight component. Only
bits [7:0] of each register are used, the remaining bits Read-As-Zero. The values in these
registers are fixed.
Table 12-31 shows the offset value, register number, and description that are associated with
each Peripheral Identification Register.
31
31 0
Reserved
4
Sub type Main class
87 3
Table 12-30 DBGDEVTYPE Register bit assignments
Bits Name Function
[31:8] - Do not modify on writes. On reads, the value returns zero.
[7:4] Subtype
0x1
, indicates that the sub-type of the device is processor core.
[3:0] Main class
0x5
, indicates that the main class of the device is debug logic.
Table 12-31 Peripheral Identification Registers
Offset (hex) Register number Function
0xFD0
1012 Peripheral Identification Register 4
0xFD4
1013 Reserved
0xFD8
1014 Reserved
0xFDC
1015 Reserved
0xFE0
1016 Peripheral Identification Register 0
0xFE4
1017 Peripheral Identification Register 1
0xFE8
1018 Peripheral Identification Register 2
0xFEC
1019 Peripheral Identification Register 3
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