Debug
ARM DDI 0363G Copyright © 2006-2011 ARM Limited. All rights reserved. 12-11
ID073015 Non-Confidential
Usage constraints The DBGDIDR Register is:
• in CP14 c0
• a 32 bit read-only register
• accessible in User and Privileged modes.
Configurations Available in all processor configurations.
Attributes See Table 12-7.
Figure 12-2 shows the DBGDIDR bit assignments.
Figure 12-2 DBGDIDR Register bit assignments
Table 12-7 shows the DBGDIDR bit assignments.
The values of the following fields of the DBGDIDR Register agree with the values in CP15 c0,
MIDR:
• DBGDIDR[3:0] is the same as CP15 c0 bits [3:0]
• DBGDIDR[7:4] is the same as CP15 c0 bits [23:20].
See c0, Main ID Register on page 4-14 for more information of CP15 c0, MIDR.
Reserved
WRP
31 28 27 24 23 20 19 16 15 4 3 0
BRP Context ID Variant Revision
Debug architecture
version
8
7
Table 12-7 DBGDIDR Register bit assignments
Bits Name Function
[31:28] WRP Number of Watchpoint Register Pairs:
b0000 = 1 WRP
b0001 = 2 WRPs
...
b0111 = 8 WRPs.
[27: 24] BRP Number of Breakpoint Register Pairs:
b0001 = 2 BRPs
b0010 = 3 BRPs
...
b0111 = 8 BRPs.
[23:20] Context Number of Breakpoint Register Pairs with context ID comparison capability:
b0000 = 1 BRP has context ID comparison capability
[19:16] Debug architecture
version
Debug architecture version:
b0100 = ARMv7 Debug.
[15:8] - RAZ.
[7: 4] Variant Implementation-defined variant number.
[3: 0] Revision Implementation-defined revision number.
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