System Control
ARM DDI 0363G Copyright © 2006-2011 ARM Limited. All rights reserved. 4-14
ID073015 Non-Confidential
4.3.2 c0, Main ID Register
The MIDR Register characteristics are:
Purpose Returns the device ID code that contains information about the processor
Usage constraints The MIDR is:
• a read-only register
• accessible in Privileged mode only.
Configurations Available in all processor configurations.
Attributes See Table 4-3 on page 4-15.
Figure 4-7 shows the MIDR bit assignments.
Figure 4-7 MIDR Register bit assignments
1 Build Options 2 Read-only
-
d
page 4-78
2-7 Undefined - - -
c3 0 Correctable Fault Location Read/write Unpredictable page 4-75
1-7 Undefined - - -
c4 0-7
c5 0 Invalidate all data cache Write-only - page 4-59
1-7 Undefined - - -
c6-c13 0-7
c15 0 c14 0 Cache Size Override Write-only - page 4-74
1-7 Undefined - - -
c15 0-7
a. The value of bits [23:20,3:0] of the MIDR depend on product revision. See the register description for more information.
b. Reset value depends on number of MPU regions.
c. Reset value depends on which caches are implemented, and their sizes.
d. See register description for more information.
Table 4-2 Summary of CP15 registers and operations (continued)
CRn Op1 CRm Op2 Register or operation Type Reset value Page
VariantImplementer
31 23 20 19 16 15 4 3 0
Architecture Primary part number Revision
24
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