ARM Cortex-R4 - Page 85

System Control
ARM DDI 0363G Copyright © 2006-2011 ARM Limited. All rights reserved. 4-15
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Table 4-3 shows the MIDR bit assignments.
Note
If an MRC instruction is executed with CRn = c0, Opcode_1 = 0, CRm = c0, and an Opcode_2 value
corresponding to an unimplemented or reserved ID register, the system control coprocessor
returns the value of the MIDR.
To access the MIDR Register, read CP15 with:
MRC p15, 0, <Rd>, c0, c0, 0 ; Read MIDR
For more information on the processor features, see The Processor Feature Registers on
page 4-18.
4.3.3 c0, Cache Type Register
The CTR characteristics are:
Purpose Determines the instruction and data minimum line length in bytes, to
enable a range of addresses to be invalidated.
Usage constraints The CTR is:
• a read-only register
• accessible in Privileged mode only.
Configurations Available in all processor configurations.
Attributes See Table 4-4 on page 4-16.
Figure 4-8 shows the CTR bit assignments.
Figure 4-8 CTR Register bit assignments
Table 4-3 MIDR Register bit assignments
Bits Name Function
[31:24] Implementer Indicates implementer:
0x41 = ARM Limited.
[23:20] Variant Identifies the major revision of the processor. This is the major revision number n in
the rn part of the rnpn description of the product revision status.
[19:16] Architecture Indicates the architecture version:
0xF = see feature registers.
[15:4] Primary part number Indicates processor part number:
0xC14 = Cortex-R4.
[3:0] Revision Identifies the minor revision of the processor. This is the minor revision number n in
the pn part of the rnpn description of the product revision status.
1CWG ERG IMinLineReserved
31 0
DMinLine 1
3413141516192028 27
Reserved
24 23