System Control
ARM DDI 0363G Copyright © 2006-2011 ARM Limited. All rights reserved. 4-18
ID073015 Non-Confidential
Table 4-6 shows the MPUIR bit assignments.
To access the MPUIR, read CP15 with:
MRC p15, 0, <Rd>, c0, c0, 4 ; Returns MPU information
4.3.6 c0, Multiprocessor ID Register
The MPIDR characteristics are:
Purpose Enables CPUs to be recognized and characterized within a multi-processor
system.
Usage constraints The MPIDR is:
• a read-only register
• accessible in Privileged mode only.
Configurations Available in all processor configurations.
Attributes Because this is a uniprocessor system, this register is Read-As-Zero.
To access the MPIDR, read CP15 with:
MRC p15, 0, <Rd>, c0, c0, 5 ; Returns Multiprocessor ID information
4.3.7 The Processor Feature Registers
The processor has two Processor Feature Registers, PFR0 and PFR1. This section describes:
• c0, Processor Feature Register 0
• c0, Processor Feature Register 1 on page 4-19.
c0, Processor Feature Register 0
The PFR0 characteristics are:
Purpose Provides information about the execution state support and programmers
model for the processor.
Usage constraints PFR0 is:
• a read-only register
• accessible in Privileged mode only.
Configurations Available in all processor configurations.
Attributes See Table 4-7 on page 4-19.
Figure 4-11 on page 4-19 shows the PFR0 bit assignments.
Table 4-6 MPUIR Register bit assignments
Bits Name Function
[31:16] - SBZ.
[15:8] DRegion Specifies the number of unified MPU regions. Set to 0, 8 or 12 data MPU regions.
[7:1] - SBZ.
[0] S Specifies the type of MPU regions, unified or separate, in the processor.
Always set to 0, the processor has unified memory regions.
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