System Control
ARM DDI 0363G Copyright © 2006-2011 ARM Limited. All rights reserved. 4-17
ID073015 Non-Confidential
Table 4-5 shows the TCMTR bit assignments.
To access the TCMTR, read CP15 with:
MRC p15, 0, <Rd>, c0, c0, 2 ; Returns TCMTR
• The ATCM and BTCM fields in the TCMTR occupy the same space respectively as the
ITCM and DTCM fields as defined by the ARM architecture. These fields, and the
corresponding TCM interfaces, can be considered equivalent to those defined in the ARM
architecture.
• The ARM architecture requires only the ITCM to be accessible from both instruction and
data sides. In the Cortex-R4 processor, both ATCM and BTCM are accessible from both
instruction and data sides.
4.3.5 c0, MPU Type Register
The MPUIR characteristics are:
Purpose Holds the value for the number of instruction and data memory regions
implemented in the processor.
Usage constraints The MPUIR is:
• a read-only register
• accessible in Privileged mode only.
Configurations Available in all processor configurations.
Attributes See Table 4-6 on page 4-18.
Figure 4-10 shows the MPUIR bit assignments.
Figure 4-10 MPUIR Register bit assignments
Table 4-5 TCMTR Register bit assignments
Bits Name Function
[31:29] - Always 0, indicating v6 format TCMTR.
[28:19] - SBZ.
[18:16] BTCM Specifies the number of BTCMs implemented. This is always set to
b001
because the processor
has one BTCM.
[15:3] - SBZ.
[2:0] ATCM Specifies the number of ATCMs implemented. Always set to b001. The processor has one ATCM.
SReserved
31 16 8 7 1 0
ReservedDRegion
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