System Control
ARM DDI 0363G Copyright © 2006-2011 ARM Limited. All rights reserved. 4-16
ID073015 Non-Confidential
Table 4-4 shows the CTR bit assignments.
To access the CTR, read CP15 with:
MRC p15, 0, <Rd>, c0, c0, 1 ; Read CTR
4.3.4 c0, TCM Type Register
The TCMTR characteristics are:
Purpose Informs the processor of the number of ATCMs and BTCMs in the system
Usage constraints The TCMTR is:
• a read-only register
• accessible in Privileged mode only.
Configurations Available in all processor configurations.
Attributes See Table 4-5 on page 4-17.
Figure 4-9 shows the TCMTR bit assignments.
Figure 4-9 TCMTR Register bit assignments
Table 4-4 CTR Register bit assignments
Bits Name Function
[31:28] - Always b1000.
[27:24] CWG Cache Write-back Granule:
0x0
= no information provided. See maximum cache line size in c0, Current Cache Size
Identification Register on page 4-34.
[23:20] ERG Exclusives Reservation Granule:
0x0
= no information provided.
[19:16] DMinLine Indicates log2 of the number of words in the smallest cache line of the data and unified caches
controlled by the processor:
0x3
= eight words in an L1 data cache line.
[15:14] - Always
0x3
.
[13: 4] - Always
0x000
.
[3: 0] IMinLine Indicates log2 of the number of words in the smallest cache line of the instruction caches
controlled by the processor:
0x3
= eight words in an L1 instruction cache line.
0
31
30
29 28 19 18 16 15 3 2 0
0 0 Reserved BTCM Reserved ATCM
To Next Page
Loading...
