System Control
ARM DDI 0363G Copyright © 2006-2011 ARM Limited. All rights reserved. 4-34
ID073015 Non-Confidential
MRC p15, 0, <Rd>, c0, c2, 5 ; Read ID_ISAR5
c0, Instruction Set Attributes Registers 6-7
ID_ISAR6 and ID_ISAR7 are not implemented, and their positions in the register map are
Reserved. They correspond to CP15 accesses with:
MRC p15, 0, <Rd>, c0, c2, 6 ; Read ID_ISAR6
MRC p15, 0, <Rd>, c0, c2, 7 ; Read ID_ISAR7
These registers are read-only, and are accessible in Privileged mode only.
4.3.12 c0, Current Cache Size Identification Register
The CCSIDR Register characteristics are:
Purpose Provides information about the size and behavior of the instruction or data
cache. Architecturally, there can be up to eight levels of cache, containing
instruction, data, or unified caches. This processor contains L1 instruction
and data caches only. The CSSELR determines which CCSIDR to select,
see c0, Cache Size Selection Register on page 4-36.
Usage constraints The CCSIDR is:
• a read-only register
• accessible in Privileged mode only.
Configurations Available in all processor configurations.
Attributes See Table 4-19.
Figure 4-23 shows the CCSIDR bit assignments.
Figure 4-23 CCSIDR Register bit assignments
Table 4-19 shows the CCSIDR bit assignments.
Line
Size
W
T
31 30 29 28 27 13 12 2 0
W
B
R
A
W
A
NumSets Associativity
Table 4-19 CCSIDR Register bit assignments
Bits Name Function
[31] WT Indicates support available for write-through:
1
= write-through support available
a
[30] WB Indicates support available for write-back:
1
= write-back support available
a
[29] RA Indicates support available for read allocation:
1
= read allocation support available
a
[28] WA Indicates support available for write allocation:
1
= write allocation support available
a
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