System Control
ARM DDI 0363G Copyright © 2006-2011 ARM Limited. All rights reserved. 4-35
ID073015 Non-Confidential
The LineSize field is encoded as 2 less than log(2) of the number of words in the cache line. For
example, a value of
0x0
indicates there are four words in a cache line, that is the minimum size
for the cache. A value of
0x1
indicates there are eight words in a cache line.
Table 4-20 shows the individual bit field and complete register encodings for the CCSIDR. Use
this to match the cache size and level of cache set by the CSSELR. See c0, Cache Size Selection
Register on page 4-36.
To access the CCSIDR read CP15 with:
MRC p15, 1, <Rd>, c0, c0, 0 ; Read CCSIDR
4.3.13 c0, Current Cache Level ID Register
The CLIDR Register characteristics are:
Purpose • Indicates the cache levels that are implemented. Architecturally,
there can be a different number of cache levels on the instruction and
data side.
• Captures the point-of-coherency.
• Captures the point-of-unification.
Usage constraints The CLIDR is:
• a read-only register
• accessible in Privileged mode only.
Configurations Available in all processor configurations.
Attributes See Table 4-21 on page 4-36.
[27:13] NumSets Indicates the number of sets as
(number of sets) - 1
a
[12:3] Associativity Indicates the number of ways as
(number of ways) - 1
a
[2:0] LineSize
Indicates the number of words in each cache line
a
a. See Table 4-20 for valid bit field encodings.
Table 4-20 Bit field and register encodings for CCSIDR
Size
Complete
register
encoding
Register bit field encoding
WT WB RA WA NumSets Associativity LineSize
4KB
0xF003E019
1111
0x001F 0x3 0x1
8KB
0xF007E019
1111
0x003F
16KB
0xF00FE019
1111
0x007F
32KB
0xF01FE019
1111
0x00FF
64KB
0xF03FE019
1111
0x01FF
Table 4-19 CCSIDR Register bit assignments (continued)
Bits Name Function
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