System Control
ARM DDI 0363G Copyright © 2006-2011 ARM Limited. All rights reserved. 4-33
ID073015 Non-Confidential
Figure 4-22 ID_ISAR4 Register bit assignments
Table 4-18 shows the ID_ISAR4 bit assignments.
To access the ID_ISAR4 read CP15 with:
MRC p15, 0, <Rd>, c0, c2, 4 ; Read ID_ISAR4
c0, Instruction Set Attributes Register 5
The ID_ISAR5 characteristics are:
Purpose Provides additional information about the properties of the processor.
Usage constraints ID_ISAR5 is:
• a read-only register
• accessible in Privileged mode only.
Configurations Available in all processor configurations.
Attributes In the processor, ID_ISAR5 is read as
0x00000000
.
To access the ID_ISAR5, read CP15 with:
SWP_frac
Exclusive
instructions
Barrier
instructions
SMC
instructions
Write-back
instructions
With shift
instructions
Unprivileged
instructions
31 24 23 20 19 16 15 12 11 8 7 4 3 0
28 27
PSR_M_instrs
Table 4-18 ISAR4 Register bit assignments
Bits Name Function
[31:28] SWP_frac RAZ because SWP/SWPB instruction support is indicated in ID_ISAR0.
[27:24] PSR_M_instrs Indicates support for M-profile instructions for modifying the PSRs:
0x0
= no support.
[23:20] Exclusive instructions Indicates support for Exclusive instructions:
0x0
= Only supports synchronization primitive instructions as indicated by bits [15:12] in the
ISAR3 register. See c0, Instruction Set Attributes Register 3 on page 4-31 for more informa-
tion.
[19:16] Barrier instructions Indicates support for Barrier instructions:
0x1
= the processor supports
DMB
,
DSB
, and
ISB
instructions.
[15:12] SMC instructions Indicates support for Secure Monitor Call (
SMC
) (formerly
SMI
) instructions:
0x0
= no support.
[11:8] Write-back instructions Indicates support for write-back instructions:
0x1
= supports all the writeback addressing modes defined in ARMv7.
[7:4] With shift instructions Indicates support for with-shift instructions:
0x4
= the processor supports:
• the full range of constant shift options, on load/store and other instructions
• register-controlled shift options.
[3:0] Unprivileged instructions Indicates support for Unprivileged instructions:
0x2
= the processor supports
LDR{SB|B|SH|H}T
and
STR{B|H}T
.
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