System Control
ARM DDI 0363G Copyright © 2006-2011 ARM Limited. All rights reserved. 4-31
ID073015 Non-Confidential
To access the ID_ISAR2 read CP15 with:
MRC p15, 0, <Rd>, c0, c2, 2 ; Read ID_ISAR2
c0, Instruction Set Attributes Register 3
The ID_ISAR3 characteristics are:
Purpose Provides information about the instruction set that the processor supports
beyond the basic set.
Usage constraints The ID_ISAR3 is:
• a read-only registers
• accessible in Privileged mode only.
Configurations Available in all processor configurations.
Attributes See Table 4-17 on page 4-32.
Figure 4-21 shows the ID_ISAR3 bit assignments.
Figure 4-21 ID_ISAR3 Register bit assignments
[11:8] Interruptible
instructions
Indicates support for multi-access interruptible instructions.
0x1
= the processor supports restartable
LDM
and
STM
.
[7:4] Memory hint
instructions
Indicates support for memory hint instructions.
0x3
= the processor supports
PLD
and
PLI
.
[3:0] Load/store
instructions
Indicates support for additional load and store instructions.
0x1
= the processor supports
LDRD
and
STRD
.
Table 4-16 ID_ISAR2 Register bit assignments (continued)
Bits Name Function
31 28 27 24 23 20 19 16 15 12 11 8 7 4 3 0
ThumbEE extension
True NOP instructions
Thumb copy instructions
Table branch instructions
Synchronization primitive instructions
SVC instructions
SIMD instructions
Saturate instructions
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