ARM Cortex-R4 - Page 100

System Control
ARM DDI 0363G Copyright © 2006-2011 ARM Limited. All rights reserved. 4-30
ID073015 Non-Confidential
Usage constraints The ID_ISAR2 is:
• a read-only register
• accessible in Privileged mode only.
Configurations Available in all processor configurations.
Attributes See Table 4-16.
Figure 4-20 shows the ID_ISAR2 bit assignments.
Figure 4-20 ID_ISAR2 Register bit assignments
Table 4-16 shows the ID_ISAR2 bit assignments.
31 28 27 24 23 20 19 16 15 12 11 8 7 4 3 0
Reversal instructions
PSR instructions
Unsigned multiply instructions
Signed multiply instructions
Multiply instructions
Interruptible instructions
Memory hint instructions
Load/store instructions
Table 4-16 ID_ISAR2 Register bit assignments
Bits Name Function
[31:28] Reversal
instructions
Indicates support for reversal instructions:
0x2 = the processor supports REV , REV16 , REVSH , and RBIT .
[27:24] PSR
instructions
Indicates support for
PSR instructions:
0x1 = the processor supports MRS and MSR , and the exception return forms of data-processing
instructions.
[23:20] Unsigned
multiply
instructions
Indicates support for advanced unsigned multiply instructions:
0x2 = the processor supports:
•
UMULL and UMLAL
• UMAAL .
[19:16] Signed
multiply
instructions
Indicates support for advanced signed multiply instructions:
0x3 = the processor supports:
•
SMULL and SMLAL
• SMLABB , SMLABT , SMLALBB , SMLALBT , SMLALTB , SMLALTT , SMLATB , SMLATT , SMLAWB , SMLAWT ,
SMULBB , SMULBT , SMULTB , SMULTT , SMULWB , SMULWT , and Q flag in PSRs
•
SMLAD , SMLADX , SMLALD , SMLALDX , SMLSD , SMLSDX , SMLSLD , SMLSLDX , SMMLA , SMMLAR , SMMLS ,
SMMLSR , SMPUL , SMPULR , SMUAD , SMUADX , SMUSD , and SMUSDX .
[15:12] Multiply
instructions
Indicates support for multiply instructions:
0x2 = the processor supports MUL , MLA , and MLS .