System Control
ARM DDI 0363G Copyright © 2006-2011 ARM Limited. All rights reserved. 4-29
ID073015 Non-Confidential
Table 4-15 shows the ID_ISAR1 bit assignments.
To access the ID_ISAR1 read CP15 with:
MRC p15, 0, <Rd>, c0, c2, 1 ; Read ID_ISAR1
c0, Instruction Set Attributes Register 2
The ID_ISAR2 is:
• a read-only register
• accessible in Privileged mode only.
The ID_ISAR2 characteristics are:
Purpose The ID_ISAR2 provides information about the instruction set that the
processor supports beyond the basic set.
Table 4-15 ID_ISAR1 Register bit assignments
Bits Name Function
[31:28] Jazelle
instructions
Indicates support for Jazelle instructions:
0x1
= the processor supports:
•
BXJ
instruction
• J bit in PSRs.
For more information see Program status registers on page 3-9 and Acceleration of execution
environments on page 3-25.
[27:24] Interworking
instructions
Indicates support for interworking instructions:
0x3
= the processor supports:
•
BX
, and T bit in PSRs
•
BLX
, and PC loads have BX behavior
• data-processing instructions in the ARM instruction set with the PC as the destination
and the S bit clear have BX-like behavior.
[23:20] Immediate
instructions
Indicates support for immediate instructions:
0x1
= the processor supports:
• the
MOVT
instruction
•
MOV
instruction encodings with 16-bit immediates
•Thumb
ADD
and
SUB
instructions with 12-bit immediates.
[19:16] ITE
instructions
Indicates support for If Then instructions:
0x1
= the processor supports
IT
instructions.
[15:12] Extend
instructions
Indicates support for sign or zero extend instructions:
0x2
= the processor supports:
•
SXTB
,
SXTB16
,
SXTH
,
UXTB
,
UXTB16
, and
UXTH
•
SXTAB
,
SXTAB16
,
SXTAH
,
UXTAB
,
UXTAB16
, and
UXTAH
.
[11:8] Exception 2
instructions
Indicates support for exception 2 instructions:
0x1
= the processor supports
RFE
,
SRS
, and
CPS
.
[7:4] Exception 1
instructions
Indicates support for exception 1 instructions:
0x1
= the processor supports
LDM
(exception return),
LDM
(user registers), and
STM
(user
registers).
[3:0] Endian
instructions
Indicates support for endianness control instructions:
0x1
= the processor supports
SETEND
and E bit in PSRs.
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