System Control
ARM DDI 0363G Copyright © 2006-2011 ARM Limited. All rights reserved. 4-28
ID073015 Non-Confidential
To access the ID_ISAR0, read CP15 with:
MRC p15, 0, <Rd>, c0, c2, 0 ; Read ID_ISAR0
c0, Instruction Set Attributes Register 1
The ID_ISAR1 characteristics are:
Purpose Provides information about the instruction set that the processor supports
beyond the basic set.
Usage constraints The ID_ISAR1 is:
• a read-only register
• accessible in Privileged mode only.
Configurations Available in all processor configurations.
Attributes See Table 4-15 on page 4-29.
Figure 4-19 shows the ID_ISAR1 bit assignments.
Figure 4-19 ID_ISAR1 Register bit assignments
[11:8] Bitfield instructions Indicates support for bitfield instructions.
0x1
= the processor supports bitfield instructions,
BFC
,
BFI
,
SBFX
, and
UBFX
.
[7:4] Bit counting instructions Indicates support for bit counting instructions.
0x1
= the processor supports
CLZ
.
[3:0] Atomic instructions Indicates support for atomic load and store instructions.
0x1
= the processor supports
SWP
and
SWPB
.
Table 4-14 ID_ISAR0 Register bit assignments (continued)
Bits Name Function
31 28 27 24 23 20 19 16 15 12 11 8 7 4 3 0
Jazelle instructions
Interworking instructions
Immediate instructions
ITE instructions
Extend instructions
Exception 2 instructions
Exception 1 instructions
Endian instructions
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