System Control
ARM DDI 0363G Copyright © 2006-2011 ARM Limited. All rights reserved. 4-27
ID073015 Non-Confidential
• c0, Instruction Set Attributes Register 2 on page 4-29
• c0, Instruction Set Attributes Register 3 on page 4-31
• c0, Instruction Set Attributes Register 4 on page 4-32
• c0, Instruction Set Attributes Register 5 on page 4-33.
c0, Instruction Set Attributes Register 0
The ID_ISAR0 characteristics are:
Purpose Provides information about the instruction set that the processor supports,
beyond the basic set.
Usage constraints The ID_ISAR0 is:
• a read-only register
• accessible in Privileged mode only.
Configurations Available in all processor configurations.
Attributes See Table 4-14.
Figure 4-18 shows the ID_ISAR0 bit assignments.
Figure 4-18 ID_ISAR0 Register bit assignments
Table 4-14 shows the ID_ISAR0 bit assignments.
Reserved
31 28 27 24 23 20 19 16 15 12 11 8 7 4 3 0
Divide instructions
Debug instructions
Coprocessor instructions
Compare and branch instructions
Bitfield instructions
Bit count instructions
Atomic instructions
Table 4-14 ID_ISAR0 Register bit assignments
Bits Name Function
[31:28] - SBZ
[27:24] Divide instructions Indicates support for divide instructions:
0x1
= the processor supports
SDIV
and
UDIV
instructions.
[23:20] Debug instructions Indicates support for debug instructions:
0x1
= the processor supports
BKPT
.
[19:16] Coprocessor instructions Indicates support for coprocessor instructions other than separately attributed
feature registers, such as CP15 registers and VFP:
0x0
= no support.
[15:12] Compare and branch
instructions
Indicates support for combined compare and branch instructions:
0x1
= the processor supports combined compare and branch instructions,
CBNZ
and
CBZ
.
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