ARM Cortex-R4 - Page 96

System Control
ARM DDI 0363G Copyright © 2006-2011 ARM Limited. All rights reserved. 4-26
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Figure 4-17 ID_MMFR3 bit assignments
Table 4-13 shows the ID_MMFR3 bit assignments.
To access the ID_MMFR3 read CP15 with:
MRC p15, 0, <Rd>, c0, c1, 7 ; Read ID_MMFR3.
4.3.11 Instruction Set Attributes Registers
The processor has eight Instruction Set Attributes Registers, ISAR0 to ISAR7, but three of these
are unused. This section describes:
• c0, Instruction Set Attributes Register 0 on page 4-27
• c0, Instruction Set Attributes Register 1 on page 4-28
Reserved Reserved
31 8 7 3 0412 11
Branch predictor maintenance operations
Hierarchical cache maintenance operations by Set and Way
Hierarchical cache maintenance operations by MVA
16 1520 1924 2328 27
Maintenance broadcast
Supersection support
Coherent walk
Table 4-13 ID_MMFR3 Register bit assignments
Bits Name Function
[31:28] Supersection support RAZ because this is a PMSA implementation.
[27:24] - SBZ
[23:20] Coherent walk RAZ because this is a PMSA implementation.
[19:16] - SBZ
[15:12] Maintenance broadcast Indicates whether cache maintenance operations are broadcast:
0x0 = cache maintenance operations only affect local structures.
[11:8] Branch predictor maintenance
operations
Indicates support for branch predictor maintenance operations in systems with hierar-
chical cache maintenance operations:
0x2 = supports invalidate entire branch predictor array and invalidate branch predictor
by MVA
a
.
[7:4] Hierarchical cache maintenance
operations by Set and Way
Indicates support for hierarchical cache maintenance operations by Set and Way:
0x1 = the processor supports invalidate cache, clean and invalidate, and clean by Set and
Way.
[3:0] Hierarchical cache maintenance
operations by MVA
Indicates support for hierarchical cache maintenance operations by address:
0x1 = the processor supports:
• Invalidate data cache by address
• Clean data cache by address
• Clean and invalidate data cache by address
• Invalidate instruction cache by address
• Invalidate all instruction cache entries.
a. Both of these operations are NOP on Cortex-R4.