System Control
ARM DDI 0363G Copyright © 2006-2011 ARM Limited. All rights reserved. 4-25
ID073015 Non-Confidential
Table 4-12 shows the ID_MMFR2 bit assignments.
To access the ID_MMFR2 read CP15 with:
MRC p15, 0, <Rd>, c0, c1, 6 ; Read ID_MMFR2.
c0, Memory Model Feature Register 3
The ID_MMFR3 characteristics are:
Purpose Provides information about the two cache line maintenance operations for
the processor.
Usage constraints The ID_MMFR3 is:
• a read-only register
• accessible in Privileged mode only.
Configurations Available in all processor configurations.
Attributes See Table 4-13 on page 4-26.
Figure 4-17 on page 4-26 shows the ID_MMFR3 bit assignments.
Table 4-12 ID_MMFR2 bit assignments
Bits Name Function
[31:28] Hardware access flag Indicates support for Hardware Access Flag:
0x0
= no support.
[27:24] WFI Indicates support for Wait-For-Interrupt stalling:
0x1
= the processor supports Wait-For-Interrupt.
[23:20] Memory barrier Indicates support for memory barrier operations:
0x2
= the processor supports:
• DSB (formerly DWB)
• ISB (formerly Prefetch Flush)
•DMB.
[19:16] TLB maintenance
operations (unified)
Indicates support for TLB maintenance operations, unified architecture:
0x0
= no support.
[15:12] TLB maintenance
operations (Harvard)
Indicates support for TLB maintenance operations, Harvard architecture:
0x0
= no support.
[11:8] L1 cache
maintenance range
operations (Harvard)
Indicates support for cache maintenance range operations, Harvard architecture:
0x0
= no support.
[7:4] L1 background
prefetch cache
operations
Indicates support for background prefetch cache range operations, Harvard
architecture:
0x0
= no support.
[3:0] L1 foreground
prefetch cache
operations
Indicates support for foreground prefetch cache range operations, Harvard
architecture:
0x0
= no support.
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