System Control
ARM DDI 0363G Copyright © 2006-2011 ARM Limited. All rights reserved. 4-24
ID073015 Non-Confidential
To access the ID_MMFR1 read CP15 with:
MRC p15, 0, <Rd>, c0, c1, 5 ; Read ID_MMFR1.
c0, Memory Model Feature Register 2
The ID_MMFR2 characteristics are:
Purpose The ID_MMFR2 provides information about the memory model, memory
management, and cache support operations of the processor.
Usage constraints The ID_MMFR2 is:
• a read-only register
• accessible in Privileged mode only.
Configurations Available in all processor configurations.
Attributes See Table 4-12 on page 4-25.
Figure 4-16 shows the ID_MMFR2 bit assignments.
Figure 4-16 ID_MMFR2 Register bit assignments
[11:8] L1 cache line maintenance
operations - Set and Way
(Harvard)
Indicates support for L1 cache line maintenance operations by Set and Way,
Harvard architecture.
0x0
= no support.
[7:4] L1 cache line maintenance
operations - MVA (unified)
Indicates support for L1 cache line maintenance operations by address, unified
architecture.
0x0
= no support.
[3:0] L1 cache line maintenance
operations - MVA (Harvard)
Indicates support for L1 cache line maintenance operations by address, Harvard
architecture.
0x0
= no support.
Table 4-11 ID_MMFR1 Register bit assignments (continued)
Bits Name Function
31 28 27 24 23 20 19 16 15 12 11 8 7 4 3 0
Hardware
access flag
WFI
Memory
barrier
TLB maintenance operations (unified)
TLB maintenance operations (Harward)
L1 cache maintenance range operations (Harward)
L1 background prefetch cache operations
L1 foreground prefetch cache operations
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