System Control
ARM DDI 0363G Copyright © 2006-2011 ARM Limited. All rights reserved. 4-23
ID073015 Non-Confidential
c0, Memory Model Feature Register 1
The ID_MMFR1 Register characteristics are:
Purpose Provides information about the memory model, memory management,
and cache support of the processor.
Usage constraints The ID_MMFR1 is:
• a read-only register
• accessible in Privileged mode only.
Configurations Available in all processor configurations.
Attributes See Table 4-11.
Figure 4-15 shows the ID_MMFR1 bit assignments.
Figure 4-15 ID_MMFR1 Register bit assignments
Table 4-11 shows the ID_MMFR1 bit assignments.
31 28 27 24 23 20 19 16 15 12 11 8 7 4 3 0
L1 test clean operations
L1 cache maintenance operations (unified)
L1 cache maintenance operations (Harvard)
L1 cache line maintenance operations - Set and Way (unified)
L1 cache line maintenance operations - Set and Way (Harvard)
L1 cache line maintenance operations - MVA (unified)
L1 cache line maintenance operations - MVA (Harvard)
Branch predictor
Table 4-11 ID_MMFR1 Register bit assignments
Bits Name Function
[31:28] Branch predictor Indicates Branch Predictor management requirements:
0x0
= no MMU present.
[27:24] L1 test clean operations Indicates support for test and clean operations on data cache, Harvard or unified
architecture:
0x0
= no support.
[23:20] L1 cache maintenance
operations (unified)
Indicates support for L1 cache, entire cache maintenance operations, unified
architecture:
0x0
= no support.
[19:16] L1 cache maintenance
operations (Harvard)
Indicates support for L1 cache, entire cache maintenance operations, Harvard
architecture:
0x0
= no support.
[15:12] L1 cache line maintenance
operations - Set and Way
(unified)
Indicates support for L1 cache line maintenance operations by Set and Way,
unified architecture:
0x0
= no support.
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