System Control
ARM DDI 0363G Copyright © 2006-2011 ARM Limited. All rights reserved. 4-22
ID073015 Non-Confidential
c0, Memory Model Feature Register 0
The ID_MMFR0 characteristics are:
Purpose The ID_MMFR0 provides information about the memory model, memory
management, and cache support operations of the processor.
Usage constraints The ID_MMFR0 is:
• a read-only register
• accessible in Privileged mode only.
Configurations Available in all processor configurations.
Attributes See Table 4-10.
Figure 4-14 shows the ID_MMFR0 bit assignments.
Figure 4-14 ID_MMFR0 Register bit assignments
Table 4-10 shows the ID_MMFR0 bit assignments.
To access the ID_MMFR0 read CP15 with:
MRC p15, 0, <Rd>, c0, c1, 4 ; Read ID_MMFR0.
31 28 27 24 23 20 19 16 15 12 11 8 7 4 3 0
Innermost
shareability
FCSE
TCM
support
PMSA VMSA
Auxiliary
Registers
Shareability
levels
Outermost
shareability
Table 4-10 ID_MMFR0 Register bit assignments
Bits Name Function
[31:28] Innermost shareability Indicates the innermost shareability domain implemented.
RAZ/UNK because only one shareability domain is implemented, see bits [15:12].
[27:24] FCSE Indicates support for Fast Context Switch Extension (FCSE):
0x0
= no support.
[23:20] Auxiliary Registers Indicates support for the auxiliary registers:
0x2
= the processor supports the Auxiliary Instruction and Data Fault Status
Registers (AIFSR and ADFSR) and the ACTLR.
[19:16] TCM support Indicates support for TCM and associated DMA:
0x1
= implementation defined.
[15:12] Shareability levels Indicates the number of shareability levels implemented:
0x0
= one level of shareability implemented.
[11:8] Outermost shareability Indicates the outermost shareability domain implemented:
0x0
= implemented as non-cacheable.
[7:4] PMSA Indicates support for Physical Memory System Architecture (PMSA):
0x3
= the processor supports PMSAv7 (subsection support).
[3:0] VMSA Indicates support for Virtual Memory System Architecture (VMSA):
0x0
= no support.
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