System Control
ARM DDI 0363G Copyright © 2006-2011 ARM Limited. All rights reserved. 4-21
ID073015 Non-Confidential
Table 4-9 shows the ID_DFR0 bit assignments.
To access the ID_DFR0 read CP15 with:
MRC p15, 0, <Rd>, c0, c1, 2 ; Read ID_DFR0
4.3.9 c0, Auxiliary Feature Register 0
The ID_AFR0 characteristics are:
Purpose Provides additional information about the features of the processor.
Usage constraints The ID_AFR0 is:
• a read-only register
• accessible in Privileged mode only.
Configurations Available in all processor configurations.
Attributes In this processor, the ID_AFR0 reads as
0x00000000
.
To access the ID_AFR0 read CP15 with:
MRC p15, 0, <Rd>, c0, c1, 3 ; Read ID_AFR0.
4.3.10 Memory Model Feature Registers
The processor has four Memory Model Feature Registers, MMFR0 to MMFR3. This section
describes:
• c0, Memory Model Feature Register 0 on page 4-22
• c0, Memory Model Feature Register 1 on page 4-23
• c0, Memory Model Feature Register 2 on page 4-24
• c0, Memory Model Feature Register 3 on page 4-25.
Table 4-9 ID_DFR0 Register bit assignments
Bits Name Function
[31:24] - SBZ.
[23:20] Microcontroller
Debug model -
memory mapped
Indicates support for the microcontroller debug model - memory mapped:
0x0
= no support.
[19:16] Trace debug model -
memory mapped
Indicates support for the trace debug model - memory mapped:
0x1
= trace supported, memory mapped access.
[15:12] Trace debug model -
coprocessor
Indicates support for the trace debug model - coprocessor:
0x0
= no support.
[11:8] Core debug model -
memory mapped
Indicates the type of embedded processor debug model that the processor supports:
0x4
= ARMv7 based model - memory mapped.
[7:4] Secure debug model Indicates the type of secure debug model that the processor supports:
0x0
= no support.
[3:0] Core debug model -
coprocessor
Indicates the type of applications processor debug model that the processor supports:
0x0
= no support.
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