ARM Cortex-R4 - Page 102

System Control
ARM DDI 0363G Copyright © 2006-2011 ARM Limited. All rights reserved. 4-32
ID073015 Non-Confidential
Table 4-17 shows the ID_ISAR3 bit assignments.
To access the ID_ISAR3 read CP15 with:
MRC p15, 0, <Rd>, c0, c2, 3 ; Read ID_ISAR3
c0, Instruction Set Attributes Register 4
The ID_ISAR4 characteristics are:
Purpose Provides information about the instruction set that the processor supports
beyond the basic set.
Usage constraints The ID_ISAR4 is:
• a read-only register
• accessible in Privileged mode only.
Configurations Available in all processor configurations.
Attributes See Table 4-18 on page 4-33.
Figure 4-22 on page 4-33 shows the ID_ISAR4 bit assignments.
Table 4-17 ID_ISAR3 Register bit assignments
Bits Name Function
[31:28] ThumbEE
extension
Indicates support for ThumbEE Execution Environment extension:
0x0 = no support.
[27:24] True NOP
instructions
Indicates support for true
NOP instructions:
0x1 = the processor supports NOP16 , NOP32 and various NOP compatible hints in both the
ARM and Thumb instruction sets.
[23:20] Thumb copy
instructions
Indicates support for Thumb copy instructions:
0x1 = the processor supports Thumb MOV(3) low register to low register.
[19:16] Table branch
instructions
Indicates support for table branch instructions:
0x1 = the processor supports table branch instructions, TBB and TBH .
[15:12] Synchronization
primitive
instructions
Indicates support for synchronization primitive instructions:
0x2 = the processor supports:
• LDREX and STREX
• LDREXB , LDREXH , LDREXD , STREXB , STREXH , STREXD , and CLREX .
[11:8] SVC instructions Indicates support for
SVC (formerly SWI ) instructions:
0x1 = the processor supports SVC .
[7:4] SIMD
instructions
Indicates support for Single Instruction Multiple Data (
SIMD ) instructions:
0x3 = the processor supports:
PKHBT , PKHTB , QADD16 , QADD8 , QASX , QSUB16 , QSUB8 , QSAX , SADD16 , SADD8 , SASX , SEL , SHADD16 ,
SHADD8 , SHASX , SHSUB16 , SHSUB8 , SHSAX , SSAT , SSAT16 , SSUB16 , SSUB8 , SSAX , SXTAB16 , SXTB16 ,
UADD16 , UADD8 , UASX , UHADD16 , UHADD8 , UASX , UHSUB16 , UHSUB8 , USAX , UQADD16 , UQADD8 , UQASX ,
UQSUB16 , UQSUB8 , UQSAX , USAD8 , USADA8 , USAT , USAT16 , USUB16 , USUB8 , USAX , UXTAB16 , UXTB16 ,
and the GE[3:0] bits in the PSRs.
[3:0] Saturate
instructions
Indicates support for saturate instructions:
0x1 = the processor supports QADD , QDADD , QDSUB , QSUB and Q flag in PSRs.