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ARM Cortex-R4 - Page 80

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System Control
ARM DDI 0363G Copyright © 2006-2011 ARM Limited. All rights reserved. 4-10
ID073015 Non-Confidential
c8-c15 0-7 Undefined - - -
1 c0 0 Current Cache Size ID Read-only
-
cd
page 4-34
1 Current Cache Level ID Read-only
-
c
page 4-35
2-7 Undefined - - -
c1-c15 0-7 Undefined - - -
2 c0 0 Cache Size Selection Read/write Unpredictable page 4-36
c1 0 c0 0 System Control Read/write
-
d
page 4-37
1 Auxiliary Control Read/write
-
d
page 4-40
2 Coprocessor Access Read/write
0x00000000
page 4-46
3-7 Undefined - - -
c1-c15 0-7
c2-c4 0 c0-c15 0-7
c5 0 c0 0 Data Fault Status Read/write Unpredictable page 4-48
1 Instruction Fault Status Read/write Unpredictable page 4-49
2-7 Undefined - - -
c1 0 Auxiliary Data Fault Status Read/write Unpredictable page 4-49
c5 0 c1 1 Auxiliary Instruction Fault
Status
Read/write Unpredictable page 4-49
2-7 Undefined - - -
c2-c15 0-7
c6 0 c0 0 Data Fault Address Read/write Unpredictable page 4-51
1 Undefined - - -
2 Instruction Fault Address Read/write Unpredictable page 4-51
3-7 Undefined - - -
c1 0 MPU Region Base Address Read/write
0x00000000
page 4-52
1 Undefined - - -
2 MPU Region Size and
Enable
Read/write
0x00000000
page 4-53
3 Undefined - - -
4 MPU Region Access
Control
Read/write
0x00000000
page 4-54
5-7 Undefined - - -
c2 0 MPU Memory Region
Number
Read/write
0x00000000
page 4-57
Table 4-2 Summary of CP15 registers and operations (continued)
CRn Op1 CRm Op2 Register or operation Type Reset value Page

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