System Control
ARM DDI 0363G Copyright © 2006-2011 ARM Limited. All rights reserved. 4-46
ID073015 Non-Confidential
To access the Secondary Auxiliary Control Register, read or write CP15 with:
MRC p15, 0, <Rd>, c15, c0, 0 ; Read Secondary Auxiliary Control Register
MCR p15, 0, <Rd>, c15, c0, 0 ; Write Secondary Auxiliary Control Register
4.3.18 c1, Coprocessor Access Register
The CPACR characteristics are:
Purpose Sets access rights for coprocessors.
Usage constraints The CPACR is:
• A read/write register.
• Accessible in Privileged mode only.
• Because this processor does not support coprocessors CP0-CP9,
CP12, and CP13, bits [27:24] and [19:0] in this register are
read-as-zero and ignore writes.
• CPACR has no effect on access to CP14, the debug control
coprocessor, or CP15, the system control coprocessor. The only
other coprocessor that the Cortex-R4F processor includes is the
FPU, CP10, and CP11. This register enables software to determine
if the FPU exists in the processor.
Configurations Available in all processor configurations.
Attributes See Table 4-26 on page 4-47.
Figure 4-29 on page 4-47 shows the CPACR bit assignments.
[2] ATCMECC
Correction for internal ECC logic on ATCM port:
d
0
= Enabled. This is the reset value.
1
= Disabled.
[1] BTCMRMW Enables 64-bit stores for the BTCMs. When enabled, the processor uses read-modify-write to
ensure that all reads and writes presented on the BTCM ports are 64 bits wide:
e
0
= Disabled
1
= Enabled.
The primary input RMWENRAM[1] defines the reset value.
[0] ATCMRMW Enables 64-bit stores for the ATCM. When enabled, the processor uses read-modify-write to
ensure that all reads and writes presented on the ATCM port are 64 bits wide:
e
0
= Disabled
1 = Enabled.
The primary input RMWENRAM[0] defines the reset value.
a. This bit is RAZ if both caches have neither ECC nor parity.
b. This bit is only supported if parity error generation is implemented in your design.
c. This bit has no effect unless the Floating Point Unit (FPU) is configured, see Configurable options on page 1-6.
d. This bit has no effect unless TCM ECC logic is configured for the respective TCM interface, see Configurable options on
page 1-6.
e. This feature is not available when the TCM interface is built with 32-bit ECC.
Table 4-25 Secondary Auxiliary Control Register bit assignments (continued)
Bits Name Function
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