System Control
ARM DDI 0363G Copyright © 2006-2011 ARM Limited. All rights reserved. 4-47
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Figure 4-29 CPACR Register bit assignments
Table 4-26 shows the CPACR bit assignments.
To access the CPACR, read or write CP15 with:
MRC p15, 0, <Rd>, c1, c0, 2 ; Read CPACR
MCR p15, 0, <Rd>, c1, c0, 2 ; Write CPACR
4.3.19 Fault Status and Address Registers
The processor reports the status and address of faults that occur during its operation. For both
data and instruction faults there are two Fault Status Registers (FSRs) and one Fault Address
Register (FAR).
Fields within the Data and Instruction FSRs indicate the priority and source of a fault and the
validity of the address in the corresponding FAR. Table 4-27 shows this encoding for the FSRs.
All other encodings for these FSR bits are Reserved.
Reserved
31 28 27 26 25 24 23
22
21
20 19 18
17
16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
cp13 cp12 cp11 cp10 cp9 cp8 cp7 cp6 cp5 cp4 cp3 cp2 cp1 cp0
Table 4-26 CPACR Register bit assignments
Bits Name Function
[31:28] - SBZ.
[27:0]
cp<n>
a
Defines access permissions for each coprocessor
Access denied is the reset condition, and is the behavior for non-existent coprocessors:
b00
= Access denied. Attempts to access generates an Undefined Instruction exception.
b01
= Privileged mode access only
b10
= Reserved
b11
= Privileged and User mode access.
Access permissions for the FPU are set by fields cp10 and cp11. For all other
coprocessor fields, the value is fixed to b00.
a. n is the coprocessor number between 0 and 13.
Table 4-27 Fault Status Register encodings
Priority Sources FSR [10,3:0] FAR
Highest Alignment 0b00001 Valid
Background 0b00000 Valid
Permission 0b01101 Valid
Synchronous External Abort 0b01000 Valid
Asynchronous External Abort 0b10110 Unpredictable
Synchronous Parity/ECC Error 0b11001 Valid
Asynchronous Parity/ECC Error 0b11000 Unpredictable
Lowest Debug Event 0b00010 Unchanged
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