System Control
ARM DDI 0363G Copyright © 2006-2011 ARM Limited. All rights reserved. 4-57
ID073015 Non-Confidential
To access the MPU Region Access Control Registers read or write CP15 with:
MRC p15, 0, <Rd>, c6, c1, 4 ; Read Region access control Register
MCR p15, 0, <Rd>, c6, c1, 4 ; Write Region access control Register
To execute instructions in User and Privileged modes:
• the region must have read access as defined by the AP bits
• the XN bit must be set to 0.
c6, MPU Memory Region Number Register
The RGNRs characteristics are:
Purpose Multiple registers with one register for each memory region implemented.
The value contained in the RGNR determines which of the multiple
registers is accessed.
Usage constraints The RGNRs are:
• Read/write register.
• Accessible in Privileged mode only.
• Writing this register with a value greater than or equal to the number
of regions from the MPUIR is Unpredictable. Associated MPU
Region Register accesses are also Unpredictable.
Configurations Use this register if the processor is configured with an MPU.
Attributes See Table 4-37.
Figure 4-36 shows the RGNR bit assignments.
Figure 4-36 RGNR Register bit assignments
Table 4-37 shows the RGNR bit assignments.
To access the RGNR, read or write CP15 with:
MRC p15, 0, <Rd>, c6, c2, 0 ; Read RGNR
MCR p15, 0, <Rd>, c6, c2, 0 ; Write RGNR
Writing this register with a value greater than or equal to the number of regions from the MPUIR
is Unpredictable. Associated MPU Region Register accesses are also Unpredictable.
Table 4-37 RGNR Register bit assignments
Bits Name Function
[31:4] - SBZ.
[3:0] Region Defines the group of registers to be accessed. Read the MPUIR to determine the number of
supported regions, see c0, MPU Type Register on page 4-17.
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