System Control
ARM DDI 0363G Copyright © 2006-2011 ARM Limited. All rights reserved. 4-56
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When TEX[2] == 1, the memory region is cacheable memory, and the rest of the encoding
defines the Inner and Outer cache policies:
TEX[1:0] Defines the Outer cache policy.
C,B Defines the Inner cache policy.
The same encoding is used for the Outer and Inner cache policies. Table 4-35 shows the
encoding.
Table 4-36 shows the AP bit values that determine the permissions for Privileged and User data
access.
010 0 0 Non-shareable Device. Device Non-shareable
010 0 1 Reserved. - -
010 1 X Reserved. - -
011 X X Reserved. - -
1BB A A Cacheable memory:
AA
c
= Inner policy
BB
c
= Outer policy
Normal
S bit
a
a. Region is Shareable if S == 1, and Non-shareable if S == 0.
b. If the memory region type is specified as Write back cacheable (no write-allocate), memory
accesses to this type of memory behave as Write Back Write Allocate behavior for a memory.
c. Table 4-35 shows the encoding for these bits.
Table 4-34 TEX[2:0], C, and B encodings (continued)
TEX[2:0] C B Description Memory Type Shareable?
Table 4-35 Inner and Outer cache policy encoding
Memory attribute encoding Cache policy
00 Non-cacheable
01 Write-back, write-allocate
10 Write-through, no write-allocate
11 Write-back, no write-allocate
Table 4-36 Access data permission bit encoding
AP bit values Privileged permissions User permissions Description
b000 No access No access All accesses generate a permission fault
b001 Read/write No access Privileged access only
b010 Read/write Read-only Writes in User mode generate permission faults
b011 Read/write Read/write Full access
b100 UNP UNP Reserved
b101 Read-only No access Privileged read-only
b110 Read-only Read-only Privileged/User read-only
b111 UNP UNP Reserved
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