ARM Cortex-R4 - Page 125

System Control
ARM DDI 0363G Copyright © 2006-2011 ARM Limited. All rights reserved. 4-55
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Figure 4-35 MPU Region Access Control Register bit assignments
Table 4-33 shows the MPU Region Access Control Registers bit assignments.
Table 4-34 shows the encoding for the TEX[2:0], C, and B regions.
Reserved BC
31 30
TEX S
12567811 1012
XN AP
Reserved
13
Table 4-33 MPU Region Access Control Register bit assignments
Bits Name Function
[31:13] - SBZ.
[12] XN eXecute Never. Determines if a region of memory is executable:
0 = all instruction fetches enabled
1 = no instruction fetches enabled.
[11] - Reserved.
[10:8] AP Access permission. Defines the data access permissions. For more information on AP bit values
see, Table 4-36 on page 4-56.
[7:6] - SBZ.
[5:3] TEX
Type extension. Defines the type extension attribute
a
.
[2] S Share. Determines if the memory region is Shared or Non-shared:
0 = Non-shared.
1 = Shared.
This bit only applies to Normal, not Device or Strongly-ordered memory.
[1] C
C bit
a
:
[0] B
B bit
a
:
a. For more information on this region attribute, see Table 4-34.
Table 4-34 TEX[2:0], C, and B encodings
TEX[2:0] C B Description Memory Type Shareable?
000 0 0 Strongly-ordered. Strongly-ordered Shareable
000 0 1 Shareable Device. Device Shareable
000 1 0 Outer and Inner write-through, no write-allocate. Normal
S bit
a
000 1 1
Outer and Inner write-back, no write-allocate.
b
Normal
S bit
a
001 0 0 Outer and Inner Non-cacheable. Normal
S bit
a
001 0 1 Reserved. - -
001 1 0
001 1 1 Outer and Inner write-back, write-allocate. Normal
S bit
a