System Control
ARM DDI 0363G Copyright © 2006-2011 ARM Limited. All rights reserved. 4-74
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Figure 4-50 VAL Debug Request Enable Clear Register bit assignments
Table 4-51 shows the VAL Debug Request Enable Clear Register bit assignments.
To access the nVAL Debug Request Enable Clear Register, read or write CP15 with:
MRC p15, 0, <Rd>, c15, c1, 7 ; Read nVAL Debug Request Enable Clear Register
MCR p15, 0, <Rd>, c15, c1, 7 ; Write nVAL Debug Request Enable Clear Register
On reads, this register returns the current setting. On writes, overflow debug requests that are
enabled can be disabled by writing a 1 to the appropriate bits.
For more information of how to enable debug requests on counter overflows, and how the
requests are signaled, see c15, VAL Debug Request Enable Set Register on page 4-69.
c15, Cache Size Override Register
The Cache Size Override Register characteristics are:
Purpose Overwrites the caches size fields in the main register. This enables you to
choose a smaller instruction and data cache size than is implemented.
Usage constraints The Cache Size Override Register is:
• a write-only register
• only accessible in Privileged mode.
Configurations Available in all processor configurations.
Attributes See Table 4-52 on page 4-75.
Figure 4-51 shows the Cache Size Override Register bit assignments.
Figure 4-51 Cache Size Override Register bit assignments
C
31 3210
Reserved
P2
P1
P0
Performance monitor counter overflow
debug request disables
Cycle count overflow
debug request disable
Table 4-51 VAL Debug Request Enable Clear Register bit assignments
Bits Name Function
[31] C PMCCNTR overflow debug request
[30:3] - UNP or SBZP
[2] P2 PMC2 overflow debug request
[1] P1 PMC1 overflow debug request
[0] P0 PMC0 overflow debug request
Icache
31 16 15 78430
Reserved
Dcache
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