System Control
ARM DDI 0363G Copyright © 2006-2011 ARM Limited. All rights reserved. 4-69
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Figure 4-45 nVAL Reset Enable Set Register bit assignments
Table 4-46 shows the nVAL Reset Enable Set Register bit assignments.
To access the nVAL Reset Enable Set Register, read or write CP15 with:
MRC p15, 0, <Rd>, c15, c1, 2 ; Read nVAL Reset Enable Set Register
MCR p15, 0, <Rd>, c15, c1, 2 ; Write nVAL Reset Enable Set Register
On reads, this register returns the current setting. On writes, interrupt requests can be enabled
by writing a 1 to the appropriate bits. If a reset request is enabled, it is disabled by writing to the
nVAL Reset Enable Clear Register. See c15, nVAL Reset Enable Clear Register on page 4-72.
If one or more of the reset request fields (P2, P1, P0, and C) is enabled, and the corresponding
counter overflows, then a reset request is indicated by nVALRESET being asserted LOW. This
signal can be passed to a system reset controller.
c15, VAL Debug Request Enable Set Register
The VAL Debug Request Enable Set Register characteristics are:
Purpose Enables any of the PMXEVCNTR Registers,
PMXEVCNTR0-PMXEVCNTR2, and PMCCNTR, to generate a debug
request on overflow. If enabled, the debug request is signaled by
VALEDBGRQ being asserted HIGH.
Usage constraints The VAL Debug Request Enable Set Register is:
• A read/write register.
• Always accessible in Privileged mode. The PMUSERENR Register
determines access in User mode, see c9, User Enable Register on
page 6-15.
Configurations Available in all processor configurations.
Attributes See Table 4-47 on page 4-70.
Figure 4-46 on page 4-70 shows the VAL Debug Request Enable Set Register bit assignments.
C
31 3210
Reserved
P2
P1
P0
Performance monitor counter
overflow reset request enables
Cycle count overflow reset request enable
Table 4-46 nVAL Reset Enable Set Register bit assignments
Bits Name Function
[31] C PMCCNTR overflow reset request
[30:3] - UNP or SBZP
[2] P2 PMC2 overflow reset request
[1] P1 PMC1 overflow reset request
[0] P0 PMC0 overflow reset request
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